Introduction to Computer Systems – Hire Academic Expert

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School of Computing Technologies
COSC2473 Introduction to Computer Systems
Assignment 2

Assessment Type: Individual assignment; no group work.
Submit online via Canvas
Assignments Assignment 2.
Clarifications/updates may be made via announcements and relevant
discussion forums.
Due Date: Week 9, Friday 23rd September 2022, 11:59pm.
Weighting: 120 marks that contributes 30% of the total assessment.

1. Overview
For this assignment you are required to
1. Demonstrate your understanding of datapath, pipelined datapath and processor architectures.
2. Perform memory design, measure and improve cache performance and demonstrate your
understanding of virtual memory.
2. Learning outcomes
This assessment is relevant to the Course Learning Outcomes CLOs 4-5.
3. Assessment details
This assessment will determine your ability to
1. Understand the concepts taught over Week 5 to Week 8 of the course.
2. Work independently in self-directed study to research the identified issues.
4. Submission
Prepare the answers to this assignment in an electronic format and convert to a single Acrobat PDF
(.pdf) file for submission, with the filename being your student number (e.g.,
containing all the answers to all the questions in this assignment.
Paper submissions are not accepted. Handwritten assignments are not accepted.
You should submit your assignment via Canvas Assignments Assignment 2 Submission. You
may resubmit the assignment if you need to, only the most recent version will be marked. Please
note the following.

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1. Clearly number each answer according to the numbering in this assignment specification (e.g.,
Q1a, Q1b, Q1c, etc.).
2. Use at least 12-point font size.
3. It is your responsibility to correctly submit your files. Please verify that your submission is
correctly submitted by downloading what you have submitted to see if your submitted file
includes the correct content.
4. Never leave submission to the last minute – you may have difficulty uploading files.
5. You can submit multiple times – a new submission will override any earlier submissions.
However, if your final submission is after the due time, late penalties will apply.
5. Academic integrity and plagiarism (standard warning)
Do not ever simply copy and paste what another writer has written. This is stealing. What we need
is your own words – your own understanding. If you try to represent someone else’s work as your
own, it will be dealt with severely. Instead, we want you to paraphrase what others have said – to
put the concepts they have discussed into your own words.
All plagiarism will be penalised, there are no exceptions and no excuses. You have been warned.
6. Rubric and marking guidelines
The rubric can be found in Canvas Assignments Assignment 2.
Submission files not in the required format will not be marked.
A penalty of 10% per day of the total available marks will apply for each day being late. After 5 days,
you will receive zero mark for the assignment.
If you want to seek an extension of time for assignment submission, you must have a substantial
reason for that, such as unexpected circumstances. Reasons such as, unable to cope with study
load, is not substantial. Also, you must apply for an extension as soon as possible. Last minute
extensions cannot be granted unless it attracts special consideration. Please find out how to apply
for special consideration online at
7. Assignment questions
This assignment has 6 questions and students are required to answer all questions.
Before You Start
Do not copy from lecture notes.
Use your own words and clearly demonstrate your understanding.

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Question 1 – Pipelining (20 marks)
Robin, Bryan, Finchie, and Dan each have messages to send via carrier pigeon. There are three
ordered stages to
sending a message via carrier pigeon:
1. 25 minutes of
Writing the message.
2. 10 minutes of
Fanning the ink dry.
3. 15 minutes of
Catching and sending a pigeon.
There is only one pen to share.
There is also only one fan (without it the ink will never dry).
There are multiple pigeons but only one can be caught at a time (They startle easily).
Fanning must happen before catching a pigeon (or it will fly off… startled)
Hint: Draw timeline diagrams to calculate the total times etc.)
a) (3 marks) How long does it take for all to send messages
b) (4 marks) How long does it take for all of them to send messages
c) (2 marks) How and why does pipelining help with the throughput of entire workloads?
The workloads involved in sending 4 messages as described above, in comparison to sending
4 messages sequentially.
d) (4 marks) Can pipelining help reduce the latency of any one step in the 4 people sending a
message scenario as described above?
Show how the pipeline rate is limited by the slowest pipeline stage.
e) (5 marks) Can you devise a better strategy if the four people given another pen and another
fan? If yes, calculate the new sending time.
f) (2 marks) What impact (if any) does the additional pen and/or fan have on the throughput
of the pipelined process of sending messages? Briefly explain your answer.
Question 2 – Datapath and pipelining performance (25 marks)
For the pipelined datapath, there are FIVE stages: IF, ID, EX, MEM and WB. Assume that each of
stages has the following latencies:

250ps 350ps 150ps 300ps 200ps

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a) (3 x 5 = 15 marks) Briefly explain what each stage does. You need to identify the functional
units involved such as PC, adder, instruction memory, register file, ALU and data memory.
b) (10 marks) Work out the ideal performance gain of the pipelined datapath over the
nonpipelined datapath. Clearly show your working and reasoning.
Question 3 – Processor architectures (15 marks)
You are a processor designer. You are tasked to design a processor for smartphones as well as
supercomputers. You have two architecture choices: RISC and CISC.
a) (6 marks) For smartphones, explain the reasons that you want to use RISC for your design
and the concerns that you may have.
b) (9 marks) For supercomputers, explain the reasons why you want to use and not use RISC.
Question 4 – Memory system design (20 marks)
You are asked to design a memory system that is fast and affordable. You have decided to take
advantage of locality and memory hierarchy for your design.
a) (8 marks) Clearly explain the effect of locality in terms of memory access. Give code
examples for your explanation (do not use the example in the lecture notes).
b) (12 marks) Clearly explain how locality and memory hierarchy work together to give a fast
and affordable memory system.
Question 5 – Cache performance (20 marks)
For a cache system with the following parameters:
Instruction cache (I-cache) miss rate = 1.5%
Data cache (D-cache) miss rate = 3%
Miss penalty = 100 cycles
Percentage of load & store instructions (the instructions that need D-cache): 30%
a) (15 marks) If it takes 1 clock cycle to complete an instruction without cache misses, that is,
cycles per instruction (CPI) is 1, what is the percentage of time that CPU will spend on
memory stalls? Show your working.
b) (5 marks) Briefly discuss how multilevel cache design improves cache performance,
assuming a two-level cache.

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Question 6 – Virtual memory (20 marks)
In virtual memory, each program has a virtual address space. A page table is used to translate from
virtual to physical memory address.
a) (2 + 2 + 4 marks) Explain the concept of virtual memory. Do you worry about if you are going
to have enough virtual memory addresses (explain your answer)? Do you worry about if you
are going to have enough physical addresses, or is there going to be any concern in terms of
performance (explain your answer)?
b) (5 + 7 marks) Assuming a cache miss, a data item is requested with its virtual memory
address. Illustrate clearly how the corresponding page is located by using the page table
directly. Explain if there are performance issues with the direct use of page table, and how
the performance can be improved.